Centre of Hardware Assurance


Hardware & Circuit Analysis

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Hardware Analysis

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X-section of an ASIC
Top view of an ASIC
Line (green traces) and contact (red ports) tracing on a 3D device
SCM amplitude of the EEPROM with content
SCM topography scan image of the EEPROM with content
Localization of specific bits in memory using a laser probe

Under the Hardware Analysis (HA) group, the overall objectives of the research area are to develop enabling ​capabilities to:

  1. ​​​​​​Analyse and validate the authenticity of integrated circuits (IC)/ field-programmable gate arrays (​FPGA) and protect our hardware against potential malicious hardware Trojans;
  2. Analyse and examine the security of advanced memory devices and protect our data against various attacks; and
  3. Retrieve and analyse digital information or aidin​g forensic analysis anchored at device/ hardware level.​

​Defence Technology Prize Individual (R&D) 2018 – Award Winner,
Professor Gan Chee Lip
​Defence Technology Prize Team (R&D) 2016 – Award Winner,

Over the years, the HA team has developed techniques to analyse and validate devices, from non-destructive techniques using 3D Computed Tomography (CT) x-ray imaging to circuit editing using Focus Ion Beam (FIB) microscopy. A range of sample preparation techniques have been developed, including laser/ acid decapsulation, chemical delayering and sample thinning. Imaging approaches being established range from optical microscopy, scanning electron microscopy to Infrared (IR) microscopy. Memory devices have been analyzed using scanning capacitance microscopy and laser stimulation. In recognition of the HA team’s significant achievements, Defence Technology Prize 2016 Team R&D Awards was presented to the Hardware Analysis and Circuit Analysis team with the collaborators.​

Circuit Analysis

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​Hierarchical Multi-Classifier Machine Learning System

The Circuit Analysis team focuses on research, design and development of advanced algorithms and tools for automatic and efficient analysis of very-large-scale integration (VLSI) digital integrated circuits and systems implemented in ASICs/ FPGAs in order to understand the functionality thereof and de​tect potential malicious alteration if any. The analysis is carried out at various layers of the VLSI circuits, including register-transfer level (RTL), logic, layout and physical, to ensure complete coverage for hardware security. Contemporary Artificial Intelligence, particularly Deep Learning techniques are extensively employed in the analysis methodologies for better adaptability and productivity. Other relevant research areas include image processing, parallel computation, graph theory and graph analysis, signal and time series analysis, optimization algorithms and formal verification.​​

Deep Learning Model for IC Image Annotation
Structure & Function Extraction of Integrated Circuits

Our team, together with the HA team and collaborators, was awarded the prestigious Defence Technology Prize 2016 for the outstanding accomplishments in R&D for enhancing the defence capabilities of Singapore. The team also received the TL@NTU Scientific Award for distinguished contributions to science and techn​​ology research in TL@NTU. The team has transited several complete electronic design automation software packages with Techno​logy readiness levels (TRL) at level 6 and above.​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​​


Prof Gan Chee Lip
Research Director (Hardware Analysis) Professor, School of Materials Science and Engineering Email: clgan@ntu.edu.sg Phone: +65 67906821
Dr Liu Qing
Programme Manager (Hardware Analysis) Senior Research Scientist Email: liuqing@ntu.edu.sg Phone: +65 65923725


Assoc Prof Gwee Bah Hwee
Research Director (Circuit Analysis) Associate Professor, School of Electrical and Electronic Engineering Email: ebhgwee@ntu.edu.sg Phone: +65 67906861
Dr Shi Yiqiong
Programme Manager (Circuit Analysis) Senior Research Scientist Email: yqshi@ntu.edu.sg Phone: +65 67906226​​​​​​​